A ferroelectric random access memory (FeRAM) generally includes an array of FeRAM cells where each FeRAM cell contains at least one ferroelectric capacitor. Each ferroelectric capacitor contains a ferroelectric material sandwiched between conductive plates. To store a data bit in a FeRAM cell, a write operation applies write voltages to the plates of the ferroelectric capacitor in the FeRAM cell to polarize the ferroelectric material in a direction associated with the data bit being written. A persistent polarization remains in the ferroelectric material after the write voltages are removed and thus provides non-volatile storage of the stored data bit.
A conventional read operation for a FeRAM determines the data bit stored in a FeRAM cell by connecting one plate of a ferroelectric capacitor to a bit line and raising the other plate to a read voltage. If the persistent polarization in the ferroelectric capacitor is in a direction corresponding to the read voltage, the read voltage causes a relatively small current through the ferroelectric capacitor, resulting in a small charge and voltage change on the bit line. If the persistent polarization initially opposes the read voltage, the read voltage flips the direction of the persistent polarization, discharging the plates and resulting in a relatively large charge and voltage increase on the bit line. A sense amplifier can determine the stored value from the resulting bit line current or voltage.
Development, manufacture, and use of an integrated circuit such as FeRAM often require testing that determines the characteristics of the integrated circuit and determines whether the integrated circuit is functioning properly. One important test for a FeRAM is measurement of the charge delivered to bit lines when reading memory cells. Generally, the bit line charge or voltage that results from reading a FeRAM cell varies not only according to the value stored in the FeRAM cell but also according to the performance of the particular FeRAM cell being read. The distribution of delivered charge can be critical to identifying defective FeRAM cells that do not provide the proper charge and to selecting operating parameters that eliminate or minimize errors when reading or writing data.
A charge distribution measurement generally tests each FeRAM cell and must measure the amount of charge read out of the FeRAM cell for each data value. Measuring the readout charge commonly requires using a sense amplifier to compare a bit line signal read from the FeRAM cell to up to 100 or more different reference levels. Each of the comparisons generates a binary signal indicating the results of the comparison. The binary comparison result signals can be output using the same data path used for read operations. Comparing the bit line voltage read from a single FeRAM cell storing a data value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d against 100 reference levels generates 100 bits of test data. Accordingly, the amount of test data generate during a distribution measurement for all cells in an FeRAM requires a relatively long time to output using the normal I/O cycle time. Charge distribution measurement for data values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d in a 4-Megabit FeRAM, for example, can generate more than 8xc3x97108 bits of test data, which may require several minutes to output. Further, the amount of test data and output time increase with memory storage capacity.
The large volume of data output from a FeRAM for a charge distribution measurement may require too much time for an efficient testing during integrated circuit manufacture. Processing the large amount of data to construct bit line voltage distributions can also create a bottleneck in a fabrication process. The amount of data can be reduce by testing only a sampling of the FeRAM cells in a FeRAM but sampling may fail to uncover some defective FeRAM cells.
In view of the current limitation of methods for measuring charge distributions of FeRAMs, structures and methods that reduce the data flow and processing burdens for measurement of charge distributions are sought. The reduced data will ideally indicate the charge distribution information but also indicate the accuracy or the amount of noise in the charge distribution information. Further, the reducing the amount of test data while retaining accuracy information would be best accomplished without requiring large or complex on-chip circuits.
In accordance with an aspect of the invention, an on-chip circuit measures the distribution of bit line voltages or charge resulting from reading FeRAM cells and compresses distribution data to reduce the amount of output data and the time required for output of the distribution data. The measurement of a bit line voltage typically involves operating a sense amplifier to compare a bit line voltage to a series of reference voltages. Instead of directly outputting result signals from the sense amplifier, a compression circuit processes the result signals to generate values indicating lower and upper limits of a range of reference voltages in which noise can cause sensing operations to provide inconsistent results. A small reference voltage range indicates that bit line voltage was accurately measured.
One embodiment of a compression circuit includes a counter and a set of registers or other storage elements connected to the counter. The counter is synchronized with changes in a reference signal input to a sense amplifier and to the series of comparisons so that the count from the counter indicates a current reference voltage that sense amplifiers are comparing to bit line voltages. Each of the storage elements corresponds to a bit line being tested and operates to store the count from the counter when the binary result values for the comparisons have a particular value. The stored value at the end of the bit line voltage measurement is a count value indicating the reference voltage (or count) that the comparisons first or last indicated as greater than the bit line voltage. To quantify noise in the comparisons, multiple count values for each bit line can be stored using different triggering conditions so that the count values indicate when more than one transition occurs in the results stream.
In one embodiment of the invention, instead of directly connecting the outputs of the sense amplifiers to enable or disable the storage elements, the output signals from the sense amplifiers control the gates of drive devices (e.g., pull-down or pull-up transistors) of a bus connected to provide enable signals to the storage elements. A precharge circuit charges the bus to a state that enables the storage devices to replace a stored value with a fresh value from the counter. Whenever a particular sense amplifier activates its associated drive device, the drive device pulls the enable signal for the corresponding storage element to a state that disables changing the stored value in the storage element. Changing the precharging scheme for the global I/O bus can provide obtain upper and lower limits for the voltage range in which noise can cause inaccurate sensing. One limit is obtained by only precharging the global I/O bus before the series of sensing operations that measure a bit line voltage. With this precharging scheme, the storage element retains the count corresponding to reference voltage just before the first sensing operation that causes the corresponding drive circuit to pull the enable signal to the disabling state. The other limit is obtain by precharging the global I/O line before each sensing operation, which causes the storage element to retain the count corresponding to the last sensing operation that failed to pull the global I/O line to the disabling state.
Another embodiment of the invention is a method for testing an integrated circuit containing FeRAM cells. The test method includes: performing sensing operations that respectively compare a series of reference voltages to a bit line voltage; generating a first data value identifying a first limit for a range of the reference voltages in which the sensing operations provided inconsistent results; and generating a second data value identifying a second limit for the range of the reference voltages in which the sensing operations provided the inconsistent results. A compression circuit in the integrated circuit can generate the first and second data values. The separation between the first and second data values indicates the accuracy of the bit line voltage measurement.
Performing the sensing operations generally generates a result signal representing a series of values with each value distinguishing whether a comparison of a corresponding one of the reference voltages to the bit line voltage indicates the reference voltage or bit line voltage is greater. The first data value can be generated from the result signal for a first series of sensing operations, by applying to a register or other storage element, a data or count signal indicating which of the reference voltages corresponds to a current value of the result signal; precharging a line providing an enable signal to the storage element, and activating a drive circuit (or pull-down transistor) for the line in response to the values of the result signal. In one test mode, precharging, which activates the enable signal to enable the storage element to set a stored value equal to a current value of the data signal, is performed only once before the first series of the sensing operations. The drive circuit when activated pulls the line to a state where the enable signal is deactivated, thereby stopping the storage element from changing the stored value. The stored value in the storage element after the first plurality of sensing operations thus identifies the first reference voltage for which a sensing operation activates the drive circuit to deactivate the enable signal, and that stored value can be the first data value.
The second data value can be generated using a different precharging scheme. In particular, for each sensing operation in a second plurality of the sensing operations, precharging the line reactivates the enable signal. With the values of the result signal corresponding to the second plurality of the sensing operations controlling the drive circuit, the storage element sets the stored value equal to a value of the data signal when the result signal does not activate the driver circuit, and the storage element maintains the stored value when the value of the result signal activates the driver circuit. At the end of the second series of sensing operations, the stored value in the storage element indicates the last reference voltage for which a sensing operation failed to activate the drive circuit, and that stored value can be the second data value.
Another method for generating test results for an integrated circuit containing FeRAM cells includes: charging a line to activate an enable signal of a storage element; performing a first series of sensing operations to generate a result signal having values indicating results of the sensing operations; applying the result signal to control a pull-down device for the line; operating a counter to generate a count value indicating which of the reference voltages corresponds to a current value of the result signal; and for each sensing operation in the first series, setting a stored value in the storage element equal to the count value in response to the enable signal being active at a time corresponding to the sensing operation, and maintaining the stored value in the storage element in response to the enable signal not being active at the time corresponding to the sensing operation. The stored value in the storage element after the first series of sensing operations can be used as a test result. Charging of the line can be limited to before the first series of sensing operations, with no further charging of the line being performed before the end of the first series of sensing operations.
The method can generate further test results using a different precharging scheme. For example, a second series of sensing operations can provide the result signal with values indicating results of the sensing operations in the second series, while charging the line activate the enable signal for each of the sensing operations in the second series. The method can then include for each sensing operation in the second series, setting the stored value in the storage element equal to the count value in response to the enable signal being active at a time corresponding to the sensing operation, and maintaining the stored value in the storage element in response to the enable signal not being active at the time corresponding to the sensing operation. The stored value in the storage element after the second series of sensing operations provides a second test result.
Yet another embodiment of the invention is an integrated circuit including a global bus, an array of FeRAM cells, a reference voltage generator, sense amplifiers, a precharge circuit, and a compression circuit. Driver devices and a precharge circuit are connected to the global bus. The reference voltage generator is operable in a test mode to generate a reference signal that sequentially has a series of reference voltages, and the sense amplifiers compare a bit line voltage to the series of reference voltages. Output signals from the sense amplifiers respectively control the driver circuits. The compression circuit includes storage elements that are respectively coupled to the global bus in the test mode, and the storage elements have an input data signal that indicates which of the reference voltages corresponds to current values of the output signals from the sense amplifiers. Signals on the global bus control whether respective storage elements are enabled to set respective stored values equal to the input data signal. For bit line voltage measurements, the precharge circuit has a first operating mode in which the precharge circuit charges the global I/O bus before each sensing operation by the sense amplifiers and has a second operating mode in which the precharge circuit charges the global I/O bus only once for a series of sensing operations by, the sense amplifiers.